A usual reminder that we're not getting smaller. This is marketting speech, transistor gates are stuck at 20ish nanometers.
What's still increasing is transistor density, but "Dennard's Scaling" is dead. we stopped decreasing voltages some time ago.
We have more transistors, so we can make smarter chips. but we can't turn them on at the same time ("dark silicon"), we don't want to melt the chips.
Short of using other materials such as GaN, frequency won't really go above 5 GHz.
There remain plenty of ways to improve performance though: improvements to system architecture (distributed, non von neumann, changing the ISA), compilers, etc. Adiabatic computing, 3D integration, carbon nanotubes, tri-gate transistors, logic in memory, "blood" (cooling + power) and other microfluiduc advances, modularization with chiplets.
The "simple" Dennard's scaling is over though, and we need to move beyond CMOS and Von Neumann to really leverage increasing density without melting away.
> A usual reminder that we're not getting smaller. This is marketting speech, transistor gates are stuck at 20ish nanometers.
A quick perusal of WikiChip seems to suggest that this isnt true. Pretty much everything is getting smaller, including Fin pitch which should directly affect transistor size (not an EE, certainly could be wrong there). You're absolutely right that terms like "7nm" have become decoupled from a specific measurement and are largely marketing terms, though.
> You're absolutely right that terms like "7nm" have become decoupled from a specific measurement and are largely marketing terms, though
Everybody says this, if I've read it once on HN, I've read it a million times.
But it bothered me, why should it be difficult to come up with a reasonably meaningful number? Just find out how many transistors can be placed in a given area, pretend they are laid out in a square, and find the number on a side, to calculate the linear density.
Well, I looked up and calculated this for several chips/processes, and I found that the number was consistently around 10 times the published figure, in nm.
The further interesting thing I discovered is that this seemed to go way back with no particular change in the ratio.
So it appears to me that the "decoupling" of the number from reality is a myth; it's not "real" but it's the same ratio it's always been.
But then, there's no obvious (to me) reason why a realistic number is out of the question, either.
> The further interesting thing I discovered is that this seemed to go way back with no particular change in the ratio.
Exactly, as that's more or less what "process node" refers to today. I guess they don't want to change the metric as some could be confused by it.
> But it bothered me, why should it be difficult to come up with a reasonably meaningful number? Just find out how many transistors can be placed in a given area, pretend they are laid out in a square, and find the number on a side, to calculate the linear density.
There are plenty of other metrics. As usual, measuring only one number hides half the story. A process node is characterized by gate leakage and capacitance among others, for the electrical characteristics. Then, more meaningful surface area metrics are the size of an actual logic cell, like SRAM or a flipflop. Some processes lend themselves to optimizations that wouldn't be visible if just placing transistors side by side.
Sorry, I should have been clearer that I was specifically talking about gate length.
Transistor size (occupied area) decreases, but that's mainly because FinFET uses vertical gates, not planar technology, so you can stack them closer (well, it also has other advantages).
Thanks for the links, that's an interesting website. If you look at the 10nm one, they explicitly call out what I said, and write 20nm for gate length (tunneling losses start increasing a lot if you reduce that, so I'm not sure how to read the 7nm page, maybe they got it wrong?)
We're not getting smaller, not that we couldn't (e-beam and ALD give us atomic resolution), but because it's useless (at that point, gate leakage and doping issues become hard to overcome).
Instead we're improving precision, and our control along the 3rd dimension. Integration technologies are also progressing: flip-chip, TSVs. That will allow features like integrated HBM, on-chip lasers and photonics circuits, etc.
What's still increasing is transistor density, but "Dennard's Scaling" is dead. we stopped decreasing voltages some time ago.
We have more transistors, so we can make smarter chips. but we can't turn them on at the same time ("dark silicon"), we don't want to melt the chips.
Short of using other materials such as GaN, frequency won't really go above 5 GHz.
There remain plenty of ways to improve performance though: improvements to system architecture (distributed, non von neumann, changing the ISA), compilers, etc. Adiabatic computing, 3D integration, carbon nanotubes, tri-gate transistors, logic in memory, "blood" (cooling + power) and other microfluiduc advances, modularization with chiplets.
The "simple" Dennard's scaling is over though, and we need to move beyond CMOS and Von Neumann to really leverage increasing density without melting away.