I work for a small trading firm. Our trading platform is on FPGA. I use SystemVerilog for both RTL and testbenches. I edit in Sublime with a SystemVerilog plugin. I use Sublime's build system to call Modelsim/Questa commands to catch errors inline. I run sims in Questa. I build with Jenkins calling Vivado Tcl scripts and use Perl to scrape the logs and timing reports to determine if a build was successful.